In a standard prior art gate array circuit, such as a programmable logic type array or other master slice type device, a plurality of input buffers are coupled between the gate array and incoming data signal lines to match the levels of the incoming data signals to the signal levels required for the gate array and to protect the gate array from noise on the data signal lines. Further, a plurality of output buffers are connected to the outputs of the gate array to amplify the gate array signals in order to drive a next stage. A simplified block diagram showing these three basic components of a gate array circuit is shown in FIG. 1. FIG. 1 includes input buffers 10, gate array 20, and output buffers 30.
A problem with prior art gate array circuits such as shown in FIG. 1 is that, since input lines 12 of input buffers 10 are usually coupled to a data bus, the various signals on the data bus will cause gates within input buffers 10 to change states, which, in turn, cause corresponding changes of state of gates within gate array 20 and output buffers 30. These changes of state occur even when the outputs of output buffers 30 are not being inspected, or, in other words, when operation of input buffers 10, gate array 20, and output buffers 30 is not required. When gates are switched, there is feed-through current during switching, and, if the next stage is a capacitive load, there is a charge current which charges the capacitive load. Consequently, when the operation of input buffers 10, gate array 20, and output buffers 30 is not required, there is a resulting wasteful use of electrical power in their operation.
This is a particular problem when a battery driven memory card is connected to a gate array circuit. In this case, the battery driven memory card uses up battery power in changing logic states within the card, as determined by the signals on a data bus, even when the operation of the memory card is not required.
Even if gate array 20 in FIG. 1 were equipped with a control terminal which disabled gate array 20 upon application of a control voltage, input buffers 10 would not be rendered inoperative and power will still be wasted by input buffers 10.
Hence, the above-described prior art gate array circuits do not allow for directly controlling the input buffers so as to only operate when needed.